Dr Nidhi Gaur

Associate Professor

Amity School of Engineering and Technology
 
  • Academic Area

    Electronics and Communication Engineering

    Computer Science and Engineering

    Telecom Engineering

  • Teaching Interests

    Data Communication and Networks (UG and PG) Real Time Operating Systems Advanced Dgital Communication Synthesis and Optimization of Digital Circuits Digital design using VHDL Programming using Verilog
  • Qualifications

    Graduation : B.Sc(-)-2003,Jiwaji University (M.P.)

    Post Graduation : M.Tech(VLSI Design)-2009,Banasthali University, Rajasthan

    Doctorate : Ph.D.(Engineering)-2021,Amity University, Noida

  • Experience

    17 Aug 2009 - Present
    Associate Professor,
    Amity School of Engineering and Technology

  • Current Courses Taught

    Embedded C

    Programming Using Verilog

    Real Time Operating Systems

  • Research Interests

    Digital Design using HDL Front end VLSI design Back end VLSI design Networking and Communication
  • Publications

    Performance Evaluation of Medium Dependence of Turbo Codes ,
    IET, Alwar

    Turbo Decoding algorithms for OFDM transmission ,
    IETE, Jaipur

    TURBO DECODING ALGORITHMS FOR OFDM TRANSMISSION ,
    Banasthali University

    Implementation of dynamic reconfigurable design on Virtex-4 FPGA ,
    Amity University

    Home security using ZigBee ,
    Amity University

    Design and Implementation of Home Monitoring System Using RF Technology ,
    IJAEEE

    Design of Smart switches using ARM Processor and RF Transreciever ,
    Excellent Publishing House

    Design and Implementation of Home Monitoring system using RF Technology ,
    IJAEEE

    Performance Evaluation of Medium Dependence of Turbo Codes ,
    IET, Alwar

    Home Security using ZIGBEE ,
    Excellent Publishing House

    Rf based smart switch control ,
    LAP Lambert publication, germany

    RF Based Smart Switch Control ,
    LAP Lambert Academic Publishing House

    MODBUS Communication in Microcontroller based elevator controller ,
    IEEE-XPLORE

    Comparison andAnalysis of AD-Hoc Routing Protocols ,
    Research India Publications

    HDL Implementation of Prepaid Electricity Billing ,
    IEEE XPLORE

    Analysis and Comparison of Leakage Power Reduction Techniques in CMOS circuits ,
    IEEE XPLORE

    OIV-CMOS: A Novel Approach towards ,
    IEEE XPLORE

    Analysis and Comparison of Leakage power Reduction Techniques in CMOS Circuits ,
    IEEE-XPLORE

    Modified Booth Multiplier Architecture Using New (1,1,1) Adder ,
    ARPN

    Hardware Efficient AES for Image Processing with High Throughput ,
    IEEE-Xplore

    A Low Power High Speed Charge Sharing LECTOR Comparator ,
    IEEE-Xplore

    Novel Power Efficient 12T Full ADDER ,
    IJSSST

    A Low Power High Speed Charge Sharing Small Swing Domino Comparator ,
    IEEE-Xplore

    Comparison of FPGA implementation of LDPC encoder algorithms ,
    IEEE-Xplore

    Performance comparison of adder architectures on 28nm FPGA ,
    IEEE Xplore

    Design and implementation of low power reservation station of a 32-bit DLX-RISC processor ,
    IEEE Xplore

    Design and implementation of 64 bit VLIW microprocessor on 20nm and 28nm technologies ,
    IEEE Xplore

    A novel implementation of 32 bit extended ALU Architecture at 28nm FPGA ,
    IEEE Xplore

    Proposed high speed 64-bit VLIW microprocessor with modified adders ,
    IEEE Xplore

    Area efficient modified booth adder based on sklansky adder ,
    IEEE Xplore

    Implementation of Area and Power Efficient Components of a MAC Unit for DSP Processors ,
    IEEE Xplore

    Enhanced AES Architecture using Extended Set ALU at 28nm FPGA ,
    IEEE Xplore

    Implementation of 9 bit Signed Vedic Multiplier on Zed Board ,
    IEEE Xplore

    Rfid and Hdl Based Pre-Paid car Parking System ,
    IEEE Xplore

    16 Bit Power Efficient Carry Select Adder ,
    IEEE Xplore

    Design and Implementation of a 32-Bit Incrementer- Based Program Counter ,
    Springer

    Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers ,
    Inderscience

    Delay efficient vedic multiplier for DSP ,
    Blue Eyes Publication

    Power and Area Efficient Vedic Multipliers Using Modified CSLA Architectures for DSP ,
    Institute of Advanced Scientific Research and 67321, Mackay Street, Deerfield Beach, Kansas City, U

    Power analysis of digital circuits for VLSI applications ,
    Blue Eyes Publication

    FFT using Power Efficient Vedic Multiplier ,
    Blue Eyes Publication

    Sleep Transistor Sizing – Impact on power performance in deep-submicron technologies ,
    RI Publications

    IoT based Air Pollution Monitoring device using Raspberry Pi and Cloud Computing ,
    IEEEXPLORE

  • Affiliations

    IET Since 01 Dec 2011

  • Conferences attended

    National Conference on Applications of Nanotecnology
    Organized By :JECRC, Jodhpur

    RASIET-O7
    Organized By :IET, Alwar

    Research and Methodology
    Organized By :AIMT

    Assessing & Developing Emotional Competencies for Effective Teaching
    Organized By :AIPAS, AUUP

    Application of information technology for business excellence
    Organized By :ONGC

    Research and Methodology
    Organized By :AUUP

    CONFLUENCE
    Organized By :ASET

    Audit by IQAC Team and post Audit Processes
    Organized By :Quality Assurance and Enhancement, AUUP

    Handling and Disposal of solid Lab Waste
    Organized By :QAE, AUUP

    Hands on workshop on LOABVIEW
    Organized By :ASET

    MECON 2013
    Organized By :ASET

    Emerging Navigation Technologies
    Organized By :ASET

    TCAD Simulation using Sentaurus tool of Synopsys
    Organized By :ASET

    SPIN 2014
    Organized By :ASET, ECE

    Custom IC Design & Device Modeling- Tools and Technologies
    Organized By :Synopsys and Eigen Technologies

    MECON 2011
    Organized By :ASET

    ANSYS HFSS Software
    Organized By :ASET

    Design of antenna and RF Devices by using high frequency Structural Simulator
    Organized By :Amity University

    INTEGRATED MANAGEMENT SYSTEM
    Organized By :AMITY UNIVERSITY

  • Short Description

    I am VLSI design Engineer. My strengths include punctuality, Hard work, Dedication toward responsibilities and Strictness towards my ethics and values. I am fond of Teaching, Management and Research. Beside this my my other interests include Poetry and creative writing in Hindi and English.